The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to the structure and etching method of interlevel metal connectors in dual damascene devices using only one photomask step.
The trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore""s xe2x80x9clawxe2x80x9d), which is still valid today after having dominated the industry for the last three decades, has several implicit consequences. First, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly. Second, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Third, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. And fourth, but not least, the best financial profit rewards were held out for the ones who were ahead in the marketplace in reaching the complexity goal together with offering the most flexible products for application.
In order to stay on course with Moore""s law, significant technological changes have been introduced in the semiconductor industry in recent years. Newer dielectric materials such as silicon-containing hydrogen silsesquioxane (HSQ) are being preferred due to their lower dielectric constant which helps to reduce the capacitance C in the RC time constant and thus allows higher circuit speed. Since the density and porosity of dielectric films affect the dielectric constant through absorption or desorption of water, films with these characteristics are introduced even when they are mechanically weaker. Films made of aerogels, organic polyimides, and parylenes fall into the same category. These materials are less dense and mechanically weaker than previous standard insulators such as the plasma-enhanced chemical vapor deposited dielectrics. This trend even affects stacks of dielectric layers such as alternating layers of plasma-generated tetraethylorthosilicate (TEOS) oxide and HSQ, or ozone TEOS oxide and HSQ. Since these materials are also used under the bond pad metal, they magnify the risk of device failure by cracking.
Furthermore, copper interconnection has been adapted to silicon integrated circuits due to its low resistance and high electromigration reliability compared to the traditional aluminum interconnection. Single-damascene and dual-damascene methods have been employed for the fabrication of copper interconnection. For multi-level copper interconnects using any of these two methods, improved electromigration reliability, especially improved lifetime of early failures have been reported, for example, in the recent article xe2x80x9cA High Reliability Copper Dual-Damascene Interconnection with Direct-Contact Via Structurexe2x80x9d (K. Ueno et al, IEEE Internat. Electron Devices Meeting 2000, December 10-13, pp. 265-268).
In spite of progress such as described in that paper, in known technology many problems still remain related to the copper interconnection concept. For example, the copper traces have to be sealed by barrier layers in order to prevent copper migration into the silicon circuitry where copper atoms are known to offer energy levels for electron recombination/generation, acting as electron life-time killers. The same sealing barriers should protect the porous insulating layers of low dielectric constant (so-called low-k materials) against intruding atoms, which may initiate coalescence of micro-voids into larger voids.
In multi-level copper metallization processes, the number of photomask steps required, together with the number of mask alignment steps, increase rapidly. This is especially true for the fabricating interlevel connectors through stacks of low-k insulating layers. The resulting steep cost increase is clearly counterproductive to the goals of Moore""s law. Little effort, however, has been dedicated in known technology to reduce the number of photomask steps. An urgent need has, therefore, arisen for a coherent, low-cost method of reducing the number of required photomask steps, especially for fabricating interlevel connectors, and, simultaneously, improve the degree of component reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.
The invention describes a method for fabricating circuit interconnects in integrated circuits comprising vertical vias and horizontal trenches between metal lines, wherein only one photomask for creating vias and trenches is needed instead of the conventional two masks. The function of the second mask is replaced by a series of plasma etch steps, which exploit differential etch rates for areas which are open relative to areas which are narrow and constricted.
In the preferred embodiment of the invention, at least one metal line is overlaid by a stack of insulating layers alternating between etch stop and dielectric layers. The method comprises the steps of depositing a layer of photoresist on the uppermost insulating layer of said stack; patterning said photoresist layer to create a plurality of structures, each structure having outer dimensions defining said trenches, and at least one hole in each trench defining said via; adjacent structures spaced at least by the diameter of said via, and aligned so that the open area between said structures is greater than the area of a single via, thereby providing differential plasma etch rates for said insulating layers, wherein the etch rate is approximately 20% greater outside said structures than inside said hole.
As a technical advantage of the invention, each interconnection created by the method of the invention is a structure of wider trenches and narrower vias, wherein the diameter of the vias is approximately the same as the narrowest width of the reverse trench pattern, and each via is centered within the trench. The reverse trench pattern surrounding the via is approximately twice the width of the via diameter.
As a further technical advantage of the invention, each interconnecting structure is spaced from an adjacent structure by at least the width of the vias. This results in a simple design rule for interconnecting structures.
In the preferred embodiment of the invention, the stack of insulating layers comprises four etch stop layers alternating with three dielectric layers. The stop layers are preferably made of silicon carbide in the thickness range from 30 to 150 nm, and the dielectric layers are preferably porous low-k materials in the thickness range from 200 to 400 nm.
The preferential etch for the stop layers comprises a plasma consisting of C4F8, argon and oxygen, at an etch rate between 100 and 200 nm/min. The preferential etch for the porous dielectric layer comprises a plasma consisting of CH3F, argon and nitrogen, at an etch rate of about 750 nm/min.
It is an aspect of the invention that the method is fully compatible with single damascene and dual damascene process flow and deep sub-micron (0.18 xcexcm and smaller) technologies.
Another aspect of the invention is that it applicable to a wide variety of circuits and process technologies. Examples of semiconductor device families include DRAMs, standard linear and logic products, digital signal processors, microprocessors, digital and analog devices, high frequency and high power devices and both large and small are chip categories.
The preferred metallization is copper; the invention is applicable, however, to a variety of metals. The invention can further be applied to any circuit where metal level-to-level interconnects are presently built with two photomasks and a process reduction to only one mask represents an economical advantage.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.